Dubbed the Tile-Mx, the multi-core processors are in development, but won't be sampling until the second half of 2016.
Company officials said the chips high core count, mesh connectivity and hardware accelerators will fix the demands on data centre and carrier networks brought on by such trends as mobility, big data, social media, the Internet of things (IoT) and the cloud.
Ezchip thinks that it will all work well with software-defined networking (SDN) and network-functions virtualization (NFV) and open switches and white boxes.
The Tile-Mx chip family is EZchip's first go with ARM architecture and means it is moving away from the proprietary designs Tilera used in building out its multi-core portfolio.
Tile-Mx will be based around Cortex-A53 cores and will be targeted at white-box networking vendors, servers that run high-performance networking applications and software vendors.
The new chip family also will include smaller versions of the chip armed with 36 and 64 ARM cores, officials said.
The new chips also will include a mesh core interconnect architecture to provide a lot of bandwidth, low latency and high linear scalability.
The chips will offer 200G-bit throughput and will be able to take advantage of the growing ARM ecosystem of open-source software vendors, officials said.