According to a posting of a processor dump by @InstLatX64 on Twitter, which was spotted by Tom's Hardware, this will mean a 3MB bump of L3 cache per core.
The Tiger Lake-U model is a quad-core with hyperthreading and the posted image also reveals that the engineering sample ran at 3.4GHz, a respectable frequency for a pre-production model.
The image confirms AVX-512 support like Sunny Cove, but it does not seem to have the avx512_bf flag that would be expected if it had supported bfloat16 like early next year’s Cooper Lake Xeon processors.
Tom's Hardware notes the specs fit with the cache redesign that Intel had mentioned for Willow Cove, the CPU core of Tiger Lake.
Tiger Lake is set to launch next year, A benchmark has also leaked out of Tiger Lake and it will feature the Gen 12 Xe graphics, which will have a new display feature and a big instruction set update.