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Intel DOCSIS 3.1 chipset faces Averna test

by on07 October 2015

Testing outfit gets top contract

Testing company Averna has been selected to test Intel's DOCSIS 3.1 chipset.

Intel has selected Averna's DP-1000 DOCSIS Protocol Analyzer to test its DOCSIS 3.1 chipset prior to final certification.

The DP-1000 captures and filters MAC-layer data in real-time to verify RF parameters, validate MAC-level communication, troubleshoot interoperability issues, and improve performance.

Developed with major industry players and designed for both DOCSIS 3.0 and DOCSIS 3.1, the DP-1000 provides users with tools for analysing, debugging, maintaining and monitoring local networks and Internet connections.

Multiple system operators (MSOs), chipset manufacturers, product developers and certifications bodies use it to quickly find and correct trouble spots in order to maintain the highest quality of service possible.

Optimised for real-time signal processing with FPGA technology, the DP-1000 analyzes up to 32x8 single or bonded US/DS channels (DOCSIS 3.0) and 2x1 OFDM US/DS channels (DOCSIS 3.1), and includes numerous channel-filtering, demodulation, triggering, display, and upgrade features.

Alex Pelland, Director of Broadband Test Strategy at Averna said that Intel wanted a solution to test its new chipset for D3.1 as well as D3.0, validate CableLabs specifications for the MAC-layer and parts of the PHY-layer, as well as evaluate CMTS interoperability.

"Our DP-1000 DOCSIS Protocol Analyzer was a perfect fit for these requirements. Since DOCSIS 3.1 will enable a new generation of sophisticated products and cable services, broadband product developers like Intel will benefit from the DP-1000's ability to accelerate the important validation and certification phases."

Last modified on 07 October 2015
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