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TSMC shows off 2nm

by on17 June 2022

Uses gate-all-around field-effect transistors

TSMC officially introduced its N2 (2nm class) manufacturing technology, its first node that will use gate-all-around field-effect transistors (GAAFETs), at its 2022 TSMC Technology Symposium.

The new fabrication process will offer a full-now performance and power benefits, but when it comes to transistor density, it will barely impress in 2025 when it comes online.

Being an all-new process technology platform, TSMC's N2 brings in two essential innovations: nanosheet transistors (which is what TSMC calls GAAFETs) and backside power rail that  serve the same goal of increasing performance-per-watt characteristics of the node.

GAA nanosheet transistors feature channels surrounded by gates on all four sides, which reduces leakage; furthermore, their channels can be widened to increase drive current and boost performance or shrunken to minimise power consumption and cost. TSMC's N2 uses backside power delivery, which the foundry considers to be among the best solutions to fight resistances in the back-end-of-line (BEOL).

TSMC's nanosheet-based N2 node can boast of a 10-15 per cent higher performance at the same power and complexity as well as a 25-30 per cent lower power consumption at the same frequency and transistor count when compared to TSMC's N3E. However, the new node increases chip density by only around 1.1X compared to N3E. In general, TSMC's N3 does offer full-node performance increases and power consumption reductions. But density-wise, the new technology can hardly impress.

TSMC's N3E node offers a 1.3X chip density increase over N5, which is a substantial increase.


Last modified on 17 June 2022
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