PCI-SIG Chairman and President Al Yanes said that new data-intensive applications were driving demand for unprecedented levels of performance
“Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the defacto standard for high performance I/O for the near future.”
Nathan Brookwood, research fellow at Insight 64. said that for 27 years, the PCI-SIG has delivered new versions of I/O standards that enable designers to accommodate the never-ending increases in bandwidth required for next generation systems, while preserving investments in prior generation interfaces and software.
“Over that period, peak bandwidth has increased from 133 MB/second (for the first 32-bit parallel version) to 32 GB/second (for the V4.0 by16 serial version), a 240X improvement. The new PCIe 5.0 standard doubles that again to 64 GB/second. We have come to take this increased performance for granted, but, it takes a coordinated effort across many members of the PCI-SIG to execute these transitions so seamlessly.”
PCIe 5.0 Specification
- Delivers 32 GT/s raw bit rate and up to 128 GB/s via x16 configuration
- Uses and adds to the PCIe 4.0 specification and its support for higher speeds via extended tags and credits
- Implements electrical changes to improve signal integrity and mechanical performance of connectors.
- Includes new backwards compatible CEM connector targeted for add-in cards.
- Maintains backwards compatibility with PCIe 4.0, 3.x, 2.x and 1.x
The new specification increases performance in the high-performance markets including artificial intelligence, machine learning, gaming, visual computing, storage, and networking.
AMD Technology & Engineering Group Corporate Fellow Gerry Talbot, AMD said the chipmaker would be bringing its first PCIe 4.0 specification CPUs to market this year and look forward to meeting the future bandwidth demands of end-users with PCIe 5.0 technology.
