The Cadence Denali DDR controller IP, and both the Denali DDR4 and LPDDR4 PHY IP, have speeds of up to 3200 Mbps, and each are in production with several customers.

Hugh Durdan, vice president of design IP at Cadence said: “Memory interface performance is crucial for alleviating the key system bottleneck of memory access, which can overshadow increases in processor performance. The high performance of Cadence's Denali DDR interface solutions supports the demanding data bandwidth requirements of various applications, including mobile, cloud computing and networking.”

The DDR4/3/3L controller and PHY IP have both dual in-line memory module (DIMM) and discrete DDR memory devices.
This solution is used for servers, RAID storage, networking processors and several other networking ASICs. The LPDDR4/3 controller and PHY IP, has been validated with both package-on-package (POP) and discrete LPDDR memory devices.

This IP solution is widely used in customer applications such as smartphones, tablets and automotive infotainment. The combination of the IP solutions' robust architecture, design guidelines and Cadence technical expertise has enabled customers to ramp their systems into volume production with DDR interfaces operating at speeds up to 3200 Mbps.

Durdan said: "We've combined our expertise with TSMC's technology to provide silicon-proven, advanced DDR IP solutions to our customers. By collaborating with TSMC on their 16FF+ process technology, Cadence enables customers to incorporate the latest DDR technology in their SoC projects while increasing their confidence in our IP solutions."

Suk Lee, TSMC senior director said that cadence was a leading IP supplier for TSMC's design ecosystem. He said:

"Through close collaboration, Cadence has developed IP for our 16FF+ advanced process node that meets the TSMC9000 silicon characterisation criteria."