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Intel reveals 3D NAND plans

by on28 May 2013

It is coming right at ya

Keyvan Esfarjani, technology & manufacturing VP at Intel and co-CEO of IM Flash Technologies (IMFT) told the Imec Technology Forum some of Chipzilla’s plans behind its 3D NAND strategy. IMFT is a joint venture between Intel and Micron and its role is to find out how to move NAND flash memory ICs into the third dimension.

Already it thinks that its development of a 20nm memory cell has bought it a generation or two of 2D scaling. Currently an industry-wide transition for the nonvolatile NAND flash memory technology from memory cells in a 2D array to strings of NAND transistors integrated vertically. But 3D memories could be arranged as a 2D array of vertical semiconductor channels with many levels of gate-all-around (GAA) structures forming the multiple voltage level memory cell transistors.

Esfarjani said that there is a scaling limit for 2D NAND flash but 2D NAND flash can scale to two more nodes at about 15 and 10nm. The first 3D NAND generation is likely to be brought up alongside that 15nm 2D node. Esfarjani added. The 16 layer NAND flash ICs will not be enough to provide an economic benefit and there will need to be 64 or at least 32 layers for it all to work.

Planar floating-gate high-K metal gate cell introduced by IMFT at the 20nm node to replace a "wrap-around" cell used at 34 and 25nm would help to scale the idea further. IMFT introduced a 128Gbit NAND flash memory at the 20nm during 2012. Meanwhile the plan is to extend the 2D NAND flash generation by using nitride film and nanodots. Esfarjani pointed out that the transition to 3-D is not limited by lithography and it could manage on a 40nm diameter semiconductor channel.

The problem is finding materials that can handle the temperatures of multi-layer semiconductor processing and the high aspect ratio etch to drive in the vertical channel.

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