The company began development on its 7nm process node in early 2014 and claimed last year that it would risk production of its 7nm process until sometime in the first half of 2017. Now, it confirms that the process will be ready for volume production one year later, with the first consumer products expected to arrive about the same time.
During a pre-show press conference before the Semicon expo in Taiwan, a senior company spokesman confirmed that TSMC is confident in the Power, Performance and Area (PPA) of its 7nm process technology and that it should outperform rivals. The company expects a majority of its growth over the next four years to stem from rising demand in smartphone, high-performance computing (HPC), Internet of Things (IoT) and automotive industries.
In April, the company already had 20 customers engaged with its 7nm process node and expects at least 15 customer tape-outs next year, following volume production of its 10nm FinFET process early next year.
As reported earlier, TSMC is also making progress in the development of its Integrated Fan-Out (InFo) wafer-level packaging (WLP) technique, allowing engineers to reduce package heights by remapping shorter pins to PCB layouts. For its current 16nm designs, this results in about a 20 percent improvement in chip performance and about a 10 percent improvement in thermal performance.
Industry faces tough decisions with significantly higher costs at 7nm
The biggest problems facing the industry right now are the astronomical costs associated with scaling down to smaller process technologies. As SemiEngineering wrote earlier this year, it costs roughly $271 million to design a 7-nanometer system on a chip, or about nine times the cost of a 28nm device. The average IC cost for a 14nm chip is about $80 million, while 10nm is $120 million for the design cost plus 60 percent for software. Meanwhile, 28nm planar runs about $30 million, according to Gartner. This presents scalability problems for smaller companies who face a costly decision of whether to adopt a 10-nanometer or 7-nanometer design schedule, or simply extend the 14nm product cycle using other creative methods.
Transistor density at 10nm and 7nm will also be different between companies, according to Intel’s Mark Bohr. In the past, transistor density was scaled by 0.7x at each node. But some companies went off-pitch by using larger interconnects with their designs in order to give customers even more Power, Performance and Area (PPA) packages. The economic trade-offs between cadences, in addition to rising chip complexity, has now shifted the traditional two-year release cycle to a longer 2.5-year cycle, according to several industry directors.
“With rising development costs and the increasing cost to migrate designs from one node to the next, we anticipate more overlap between nodes as the industry tries to maximize returns from investments made at each node,” says Yang Pan, CTO of Global Products at Lam Research. “Chipmakers targeting different applications and serving different markets will have varying strategies in adopting these leading-edge nodes.”