Lots more integration
Last modified on Tuesday, 17 June 2008 19:11
Intel has released more information on its Nehalem range.
Rajesh Kumar, Intel fellow and Director of the Circuit and Low Power Technologies Digital Enterprise Group, has released a few more details about the chips which will use Intel's next-generation chip architecture. The details reveal some of the major data transfer and power savings goals for Nehalem.
Kumar said that Nehalem integrates more components, including the memory controller, to get lower latency to memory, and much higher bandwidth to memory. He claimed that Nehalem will deliver 25 Gigabytes per second for socket-to-socket communication and 32-Gigabytes per second going to main memory. This will be three times faster than any competition.