Featured Articles

AMD sheds light on stacked DRAM APUs

AMD sheds light on stacked DRAM APUs

AMD is fast tracking stacked DRAM deployment and a new presentation leaked by the company  points to APUs with stacked DRAM,…

More...
Nvidia officially launches the 8-inch Shield Tablet

Nvidia officially launches the 8-inch Shield Tablet

As expected and reported earlier, Nvidia has now officially announced its newest Shield device, the new 8-inch Shield Tablet. While the…

More...
Intel launches new mobile Haswell and Bay Trail parts

Intel launches new mobile Haswell and Bay Trail parts

Intel has introduced seven new Haswell mobile parts and four Bay Trail SoC chips, but most of them are merely clock…

More...
Aerocool Dead Silence reviewed

Aerocool Dead Silence reviewed

Aerocool is well known for its gamer cases with aggressive styling. However, the Dead Silence chassis offers consumers a new choice,…

More...
AMD A8-7600 Kaveri APU reviewed

AMD A8-7600 Kaveri APU reviewed

Today we'll take a closer look at AMD's A8-7600 APU Kaveri APU, more specifically we'll examine the GPU performance you can…

More...
Frontpage Slideshow | Copyright © 2006-2010 orks, a business unit of Nuevvo Webware Ltd.
Tuesday, 28 May 2013 10:19

Intel reveals 3D NAND plans

Written by Nick Farrell



It is coming right at ya

Keyvan Esfarjani, technology & manufacturing VP at Intel and co-CEO of IM Flash Technologies (IMFT) told the Imec Technology Forum some of Chipzilla’s plans behind its 3D NAND strategy. IMFT is a joint venture between Intel and Micron and its role is to find out how to move NAND flash memory ICs into the third dimension.

Already it thinks that its development of a 20nm memory cell has bought it a generation or two of 2D scaling. Currently an industry-wide transition for the nonvolatile NAND flash memory technology from memory cells in a 2D array to strings of NAND transistors integrated vertically. But 3D memories could be arranged as a 2D array of vertical semiconductor channels with many levels of gate-all-around (GAA) structures forming the multiple voltage level memory cell transistors.

Esfarjani said that there is a scaling limit for 2D NAND flash but 2D NAND flash can scale to two more nodes at about 15 and 10nm. The first 3D NAND generation is likely to be brought up alongside that 15nm 2D node. Esfarjani added. The 16 layer NAND flash ICs will not be enough to provide an economic benefit and there will need to be 64 or at least 32 layers for it all to work.

Planar floating-gate high-K metal gate cell introduced by IMFT at the 20nm node to replace a "wrap-around" cell used at 34 and 25nm would help to scale the idea further. IMFT introduced a 128Gbit NAND flash memory at the 20nm during 2012. Meanwhile the plan is to extend the 2D NAND flash generation by using nitride film and nanodots. Esfarjani pointed out that the transition to 3-D is not limited by lithography and it could manage on a 40nm diameter semiconductor channel.

The problem is finding materials that can handle the temperatures of multi-layer semiconductor processing and the high aspect ratio etch to drive in the vertical channel.

blog comments powered by Disqus

 

Facebook activity

Latest Commented Articles

Recent Comments