Featured Articles

Hands on: Nvidia Shield Tablet with Android 5.0

Hands on: Nvidia Shield Tablet with Android 5.0

We broke the news of Nvidia's ambitious gaming tablet plans back in May and now the Shield tablet got a bit…

More...
Nokia N1 Android tablet ships in Q1 2015

Nokia N1 Android tablet ships in Q1 2015

Nokia has announced its first Android tablet and when we say Nokia, we don’t mean Microsoft. The Nokia N1 was designed…

More...
Marvell launches octa-core 64-bit PXA1936

Marvell launches octa-core 64-bit PXA1936

Marvell is better known for its storage controllers, but the company doesn’t want to give up on the smartphone and…

More...
TSMC 16nm FinFET Plus in risk production

TSMC 16nm FinFET Plus in risk production

TSMC’s next generation 16nm process has reached an important milestone – 16nm FinFET Plus (16FF+) is now in risk production.

More...
Nvidia GTX 970 SLI tested

Nvidia GTX 970 SLI tested

Nvidia recently released two new graphics cards based on its latest Maxwell GPU architecture, with exceptional performance-per-watt. The Geforce GTX 970…

More...
Frontpage Slideshow | Copyright © 2006-2010 orks, a business unit of Nuevvo Webware Ltd.
Monday, 20 February 2012 16:44

VIA getting into SSD design

Written by Nick Farrell



It is the newest bandwagon to jump on


VIA appears to be thinking that there is money to be made in SSD design.

We got a clue this morning when an outfit called Tensilica sent us a press release saying that VIA has selected Tensilica's Xtensa dataplane processors (DPUs) for a system-on-chip (SOC) design for solid state drives (SSDs). VIA felt that Tensilica's DPUs would provide over four times the performance of competing processors on key algorithms used to benchmark competitive alternatives and went for it.

But what this seems to be telling us is that VIA has worked out that there is shedloads to be made on the back of SSDs Tensilica's DPUs allow designers to customize the IP core, mix both control and signal processing, and add high-bandwidth connectivity to increase performance without increasing the clock speed. For example, designers can use single-cycle bit field manipulation and arithmetic instructions along with multiple simultaneous single-cycle table lookups to achieve over 10 times the efficiency of other processors. This not only increases IOPS, but also significantly reduces the energy consumed and the complexity of the SOC design itself.

Jiin Lai, VIA's CTO is expecting a lot of competition an the SSD market and he thinks there is a significant advantage using Tensilica DPUs to lower the power and increase the throughput of his  products.

Nick Farrell

E-mail: This e-mail address is being protected from spambots. You need JavaScript enabled to view it
blog comments powered by Disqus

 

Facebook activity

Latest Commented Articles

Recent Comments