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Tuesday, 29 November 2011 10:39

Lattice releases new low power technology

Written by Nick Farell



Lattice pray


Lattice Semiconductor has released a new generation of its LatticeECP4 FPGA family which targets the low cost, low power mid-range FPGA (field-programmable gate array) market.

According to Silicon India the fourth generation Lattice ECP4 has a 6 Gbps Serializer/Deserializer (SERDES) in low cost wire-bond packages, souped up  digital signal processing (DSP) blocks and hard IP-based communication engines. This should sit it in the middle of a market which is looking for cheap and power sensitive wireless, wire line, video hardware. The ECP4's lower power architecture is tuned for mid-density devices and the outfit claims that its modified logic routing power ratio helps achieve higher performance with only a modest dynamic power increase. It also features higher bandwidth and performance.

We should see the chips in remote wireless radio heads, distributed antenna systems, cellular base stations, Ethernet aggregation, switching, routing, industrial networking, video signal processing, video transmission and data centre computing. It contains up to 16 CEI-Compliant 6 Gbps SERDES channels with embedded physical coding sub-layer (PCS) blocks in both low cost wire-bonded and high performance flip chip packages. This means that punters have a choice to use the LatticeECP4 FPGA in a chip to chip arrangement as well as long reach backplane applications.

It's  DSP blocks have 18x18 multipliers, wide ALUs, adder-trees [snakes don't grow on trees. Ed] and carry chains for cascade ability. Lattice claims that its ECP4 is up to 50 percent faster than its previous device and it features 1066 Mbps DDR3 memory interfaces and 1.25 Gbps low-voltage differential signaling input and outputs that are also capable of being used as serial gigabit Ethernet interfaces. The gear also has 66 percent more logic resource and 42 percent more embedded memory to empower design engineers to constructs complete systems on chip in FPGAs.

Device samples will be available in the first half of 2012 and high-volume production delivery is scheduled for the second half of 2012, the outfit said.

Nick Farell

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Comments  

 
0 #1 Kryojenix 2011-11-29 22:49
This article is way too technical for me to understand, but I do know that you don't need that apostrophe in the "Its" at the beginning if the fourth paragraph. ;-)
 

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