German-based Computerbase has spotted a few interesting details about AMD's upcoming Bulldozer CPU. The chaps spotted that at ISSCC 2011 conference, between 20th and 24th of February, AMD plans to talk a bit more about its Bulldozer architecture.
The interesting part is that the chip should work at 3.5GHz or a bit more and with the help of Turbo (Turbo Core 2 ) it should be able to overclock its cores for additional 500MHz making it to 4GHz. It will need between 0.8 and 1.3V which looks good and the chip as you might know by now has 8MB L3 cache.
The Bulldozer module consists of two Integer cores with total of 213 million transistors while some parts of the chip get shared. This saves you some transistors but might bring some additional problems, like more heat, we’ve learned.
Here is what AMD will be saying at ISSCC 2011:
“The Bulldozer 2-core CPU module contains 213M transistors in an 11-metal layer 32nm high-k metalgate SOI CMOS process and is designed to operate from 0.8 to 1.3V. This micro-architecture improves performance and frequency while reducing area and power over a previous AMD x86-64 CPU in the same process. The design reduces the number of gates/cycle relative to prior designs, achieving 3.5GHz+ operation in an area (including 2MB L2 cache) of 30.9mm2 …
An 8MB level 3 cache, composed of 4 independent 2MB subcaches, is built on a 32nm SOI process. It features column-select aliasing to improve area efficiency, supply gating and floating bit lines to reduce leakage power, and centralized redundant row and column blocks to improve yield and testability. The cache operates above 2.4GHz at 1.1V. ….”
Eight-core Bulldozer at 32nm aims for 852 Million transistors and probably some other parts will take a bit more. Have in mind that six core Thuban at 45nm has 904 million transistors on a 346 square millimeter die. The twelve core server version is looking at 1278 million transistors if not a tad more.
The ISSCC program is here. (PDF)Also read