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Frontpage Slideshow | Copyright © 2006-2010 orks, a business unit of Nuevvo Webware Ltd.
Tuesday, 04 November 2008 07:07

Core i7 965 in the lab reaches 4GHz - 3 Cache, Memory

Written by Eliot Kucharik

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Preview: New Architecture with tricky settings



Cache:

Another disadvantage was the way their Quads were built by sticking two dual-cores on a chip, where interconnecting two chips is an easy way, but the communication with the memory controller introduces quite huge latencies. So, Intel went again the AMD path and developed a native quad-core, with a similar cache layout as its rival. Introducing an L3 cache which, of course, is slower compared the massive 2x6MB L2 cache on the QX Quads and because it's only clocked x20 which gives you only 2.66GHz compared to the nominal 3.2GHz of the i7 965 Extreme. A smaller cache also saved a lot of transistors which, on the other hand, increases yield and therefore reduces costs. The transistor count went down from 820 million to 731 million.

To improve performance the L1 caches have now 3 instead of 4 cycles latency, the L2 cache increases from 11 to 15 cycles and the new L3 cache needs 39 cycles. On the other hand, the TLB was increased to 64 entries from previous 16 and the memory controller in the CPU itself reduces latencies about 50% compared to the previous access via FSB to the Northbridge chip. Overall, this decision should not impact performance, in the worst case scenario it is only slightly behind the predecessors, while in most cases it's faster, because there are only few applications which would fit into the 6MB L2 cache of a Penryn CPU.

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Memory Controller:

For some reason Intel decided to design a triple-channel memory controller. We think the memory subsystem is antique at best and a real new solution should have taken place, because the step from DDR2 to DDR3 is quite minor and inadequate as we have proved a long time ago here. While DDR3 offers better power-consumption this advantage is neglected by high-speed modules which go as high as 2.1V. At least now memory companies go the right way introducing higher speed modules with lower voltage requirements, due to the fact Intel stated their internal memory controller can't handle more than 1.65V, otherwise you may damage the CPU. Board vendors will circumvent this by introducing memory voltage controllers decoupled from the CPU, but in the OEM market such costs will always be avoided.

A third channel gives you only 8.5GB/s bandwidth, while the dual-channel interleaving gives you the full bandwidth of 25.6GB/s. To make it work better, Intel would have needed a quad-channel interface, but you know space is limited on mainboards and they won't introduce a new board-size standard after their fiasco with BTX. We will, of course, show you if there's any performance difference by going triple-channel over dual-channel in the review.

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Last modified on Thursday, 06 November 2008 04:55
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