Featured Articles

HP Stream is a Chromebook killer priced at $200

HP Stream is a Chromebook killer priced at $200

We have been hearing reports of a new breed of affordable Windows notebooks for months. It is alleged that a number…

More...
AMD Radeon R7 SSD line-up goes official

AMD Radeon R7 SSD line-up goes official

AMD has officially launched its first ever SSDs and all three are part of AMD’s AMD Radeon R7 SSD series.

More...
KitKat has more than a fifth of Android users

KitKat has more than a fifth of Android users

Android 4.4 is now running on more than a fifth of Android devices, according to Google’s latest figures.

More...
Aerocool Dead Silence reviewed

Aerocool Dead Silence reviewed

Aerocool is well known for its gamer cases with aggressive styling. However, the Dead Silence chassis offers consumers a new choice,…

More...
Frontpage Slideshow | Copyright © 2006-2010 orks, a business unit of Nuevvo Webware Ltd.
Thursday, 12 July 2007 11:23

IBM creates new stable SRAM

Written by David Stellmack
Image

Memory beyond 6GHz
IBM has unveiled a prototype embedded SRAM chipset that is capable of reaching speeds beyond 6 GHz, nearly two times the speed of currently available SRAMs. Embedded SRAMs hold data that is frequently accessed by the processor. The faster the access, the faster the data transfer from SRAM to CPU.

Researchers have long sought methods to overcome the effects of process variability, especially variations in the device turn-on characteristics when a device is placed among an array of other devices. Those device variations can cause loss of stored data, rendering the devices "unstable."

IBM researchers have discovered a novel hardware-based solution to eliminate "half select" problems, improve Vmin and increase performance for multi-port applications by using 8T SRAM arrays. Half-select occurs when the ‘word line’ is “on” and ‘column select’ is “off,” which leads to instability.

A novel write-byte concept generates ‘local-write word’ lines, which are only selected when the ‘write control’ for the selected block is “on,” avoiding half-select disturb conditions. Thus, the separate read port eliminates half-select during ‘read,’ and write byte eliminates half-select during ‘write.’
Last modified on Thursday, 12 July 2007 11:44
blog comments powered by Disqus

 

Facebook activity

Latest Commented Articles

Recent Comments