Featured Articles

Snapdragon 400 is Qualcomm’s SoC for watches, wearables

Snapdragon 400 is Qualcomm’s SoC for watches, wearables

We wanted to learn a bit more about Qualcomm's plans for wearables and it turns out that the company believes its…

More...
Qualcomm sampling 20nm Snapdragon 810

Qualcomm sampling 20nm Snapdragon 810

We had a chance to talk to Michelle Leyden-Li, Senior Director of Marketing, QCT at Qualcomm and get an update on…

More...
EVGA GTX 970 SC ACX 2.0 reviewed

EVGA GTX 970 SC ACX 2.0 reviewed

Nvidia has released two new graphics cards based on its latest Maxwell GPU architecture. The Geforce GTX 970 and Geforce GTX…

More...
Nvidia GTX 980 reviewed

Nvidia GTX 980 reviewed

Nvidia has released two new graphics cards based on its latest Maxwell GPU architecture. The Geforce GTX 970 and Geforce GTX…

More...
PowerColor TurboDuo R9 285 reviewed

PowerColor TurboDuo R9 285 reviewed

Today we will take a look at the PowerColor TurboDuo Radeon R9 285. The card is based on AMD’s new…

More...
Frontpage Slideshow | Copyright © 2006-2010 orks, a business unit of Nuevvo Webware Ltd.
Thursday, 12 July 2007 11:23

IBM creates new stable SRAM

Written by David Stellmack
Image

Memory beyond 6GHz
IBM has unveiled a prototype embedded SRAM chipset that is capable of reaching speeds beyond 6 GHz, nearly two times the speed of currently available SRAMs. Embedded SRAMs hold data that is frequently accessed by the processor. The faster the access, the faster the data transfer from SRAM to CPU.

Researchers have long sought methods to overcome the effects of process variability, especially variations in the device turn-on characteristics when a device is placed among an array of other devices. Those device variations can cause loss of stored data, rendering the devices "unstable."

IBM researchers have discovered a novel hardware-based solution to eliminate "half select" problems, improve Vmin and increase performance for multi-port applications by using 8T SRAM arrays. Half-select occurs when the ‘word line’ is “on” and ‘column select’ is “off,” which leads to instability.

A novel write-byte concept generates ‘local-write word’ lines, which are only selected when the ‘write control’ for the selected block is “on,” avoiding half-select disturb conditions. Thus, the separate read port eliminates half-select during ‘read,’ and write byte eliminates half-select during ‘write.’
Last modified on Thursday, 12 July 2007 11:44
blog comments powered by Disqus

 

Facebook activity

Latest Commented Articles

Recent Comments