Back in April we mentioned that Shanghai and Montreal are the K10 successor codenames. Yesterday at analyst day in New York, Mario Rivas has confirmed the existence of these two.
Shanghai is the next quad core that comes to save Barcelona's K10 bottom. This is an improved K10 design that AMD insiders also call K10.5, and this new chipset will have 512KB L2 cache per core. It is a native quad core design, but it will have 6MB L3 cache. Barcelona / Agena K10 has only 2MB.
The new 45nm chipset will use RDDR2 memory, 3x Hypertransport 1, will have IPC enhancements and support for AMD-V. According to AMD's current plan, it expects to ship Shanghai in 2H 2008.
Montreal is the next generation chip and it will come with octal or quad core design. It will have 1MB L2 memory per core, 6 to 12MB L3. It supports DDR3 memory, 4X Hypertransport 3 and AMD-V. As far as we know, Octal core design will be based on two quad cores stitched together. Montreal comes in 2H 2009.
AMD plans to have this in the first half of 2008; again, later than Intel, as by this time Intel should have Nehalem quad and even octal cores out.
Montreal is AMD's octa core April 2007
AMD's Shanghai K10.5 has 6 MB L3 cache April 2007
Published in Processors
AMD confirms Shanghai quad and Montreal octal core
by Fuad Abazovic on14 December 2007
Quad and octal cores