Published in Processors

TSMC preparing 12nm process technology

by on30 November 2016

A smaller version of existing 16nm technology

According to industry sources, TSMC is planning to introduce a 12 nanometer half-node process to enhance competition with 28nm and lower process nodes that have been adopted over the past few years.

The chip manufacturer’s 12nm process node will join its existing 16nm process portfolio as a smaller option in order to give it a competitive advantage against Samsung and GlobalFoundries. It is expected to offer improved leakage characteristics at a lower cost than its 16nm lineup. TSMC currently offers three variants of its 16nm FinFET process designed both for high-performance devices, as well as for ultra-low power situations requiring less than 0.6 volts.

Back in September, GlobalFoundries was the first to announce a 12nm process using Fully Depleted Silicon-On-Insulator (FD-SOI) planar technology. The foundry claims that 12FDX can deliver “15 percent more performance over current FinFET technologies” with “50 percent lower power consumption,” at a cost lower than existing 16nm FinFET devices.

TSMC currently supplies 16nm chips to a number of American, Chinese and Taiwanese companies including Apple, Nvidia, Xilinx, Spreadtrum and MediaTek, while GlobalFoundries provides chips using 14nm FinFET technology for AMD’s Polaris graphics cards and upcoming Zen processors. Meanwhile, Samsung provides 14nm LPP technology to Qualcomm for its Snapdragon 820 series and for use in its own mobile device lineup.

Although TSMC’s 12nm process was originally planned to be introduced as a fourth-generation 16nm optimization, it will now be introduced as an independent process technology instead. Three of the company’s partners have already received tape-outs on 10nm designs and the process is expected to start generating revenues by early 2017. Apple and MediaTek are likely to be the first with 10nm TSMC-based products, while the 12nm node should become a useful enhancement to fill the competition gap before more partners are capable of building 10nm chips.

Last modified on 30 November 2016
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