The announcements were made at a TSMC house event, the 2021 Online OIP Ecosystem Forum.
It looks like N3 will offer customers the kind of performance improvements they might hope for from a major node jump, though the speed improvement will be at the low-end of TSMC’s projected aspirations from last year
The foundry highlighted the participation of its EDA partners in helping to support the N3 node, to assure eager chip designers that the tools to design and test ICs for N3 will be ready and available.
L.C. Lu, TSMC’s vice president of its design and technology platform, presented the details about the company’s updated manufacturing capabilities. N4, the “easy migration path from N5”, will start volume production this year, and provide a six per cent decrease in die area. It is, as it was intended and advertised to be, a modest shrink.
Lu started by offering some historical statistics about the jump from N7 to N5, providing perspective for the coming improvements from N5 to N3 (see accompanying table, above right). The logic density improvement in the latest node jump will be less than the density improvement in the previous one — and less than hoped for. The speed improvement will also be less this time around, but at least the number was in the target range.
The benchmark for comparisons was an Arm A72 core. Lu said the numbers will certainly be different for different products, but that the results achieved with the ARM core will be a good reference for other product designs.
TSMC has been tweaking the processes at each node for specific end uses, particularly high-performance computing. HPC customers should ask for the N3 DTCO node variant. Lu said that when going from N5 to N3, customers would get a 10 per cent speed boost at 26 per cent less power.
Going from N5 to N3 DTCO would get a 22 percent increase, however, but at only 16 percent less power. So, designers can get additional speed at the expense of power efficiency.
Lu said the extra 12 percent in speed comes from resizing cells (they’re taller) which reduces source resistance a new cell structure specifically for HPC that include faster flip-flops and a via pillar and a new metal design: BEOL MiM (back end of line, metal-insulator-metal).
TSMC’s N3 DTCO node includes optimisations specifically for high-performance computing, or HPC.