Transactional Synchronization Extensions (TSX) have been around since Haswell for hardware transactional memory support. Going off Intel’s past numbers TSX can be about 40 percent faster in specific workloads or as much as five times faster in database transaction benchmarks.

However, TSX issues are rather good for possible side-channel timing attacks that could lead to KASLR being defeated and CVE-2019-11135 (TSX Async Abort) for an MDS-style flaw.

Intel is disabling TSX by default across multiple families of Intel CPUs from Skylake through Coffee Lake. The Linux kernel is preparing for this microcode change, as seen in the flow of new patches this morning for the 5.14 merge window.

A memory ordering issue is what is reportedly leading Intel to now deprecate TSX on various processors. An  Intel whitepaper outlines the problem. The memory ordering issue has been known to Intel since October 2018 but only now in June 2021 are they pushing out microcode updates to disable TSX by default.

With forthcoming microcode updates will effectively deprecate TSX for all Skylake Xeon CPUs prior to Stepping 5 (including Xeon D and 1st Gen Xeon Scalable), all 6th Gen Xeon E3-1500m v5 / E3-1200 v5 Skylake processors, all 7th/8th Gen Core and Pentium Kaby/Coffee/Whiskey CPUs prior to 0x8 stepping, and all 8th/9th Gen Core/Pentium Coffee Lake CPUs prior to 0xC stepping will be affected. That ultimately spans from various Skylake steppings through Coffee Lake; it was with 10th Gen Comet Lake and Ice Lake where TSX/TSX-NI was subsequently removed.

In addition to disabling TSX by default and force-aborting all RTM transactions by default, a new CPUID bit is being enumerated with the new microcode to indicate that the force aborting of RTM transactions.

Linux and other operating systems applied a workaround for the TSX memory ordering issue but now when this feature is disabled, the kernel can drop it. These patches are coming with the Linux 5.14 cycle and will likely be back-ported to stable too.