Featured Articles

Analysts expect ARM to do well next year

Analysts expect ARM to do well next year

British chip designer ARM could cash in on the mobile industry's rush to transition to 64-bit operating systems and hardware.

More...
Huawei and Xiaomi outpace Lenovo, LG in smartphone market

Huawei and Xiaomi outpace Lenovo, LG in smartphone market

Samsung has lost smartphone market share, ending the quarter on a low note and Xiaomi appears to be the big winner.

More...
Intel Broadwell 15W coming to CES

Intel Broadwell 15W coming to CES

It looks like Intel will be showing off its 14nm processors, codenames Broadwell, in a couple of weeks at CES 2015.

More...
Gainward GTX 980 Phantom reviewed

Gainward GTX 980 Phantom reviewed

Today we’ll be taking a closer look at the recently introduced Gainward GTX 980 4GB with the company’s trademark Phantom cooler.

More...
Zotac ZBOX Sphere OI520 barebones vs Sphere Plus review

Zotac ZBOX Sphere OI520 barebones vs Sphere Plus review

Zotac has been in the nettop and mini-PC space for more than four years now and it has managed to carve…

More...
Frontpage Slideshow | Copyright © 2006-2010 orks, a business unit of Nuevvo Webware Ltd.
Thursday, 10 May 2007 09:39

All K10 features listed

Written by Fuad Abazovic
Image

20 secrets revealed

The AMD 10h processor family - also known as K10 - has 20 key features. We will put them all on paper for you. Some of them are known, but some of them are not. Let's list them.

First of all, the K10 has an integrated DDR2 memory controller with memory prefatcher and the K10 core has 64kb of L1 instruction cache + 64 KB data cache. It also has on chip L2 and L3 cache and this varies depending on the core. The Barcelona / Agena quad core K10 for example has 4x512 KB L2 and 2 MB of L3 cache. K10 supports 32 Byte instruction fetch, instruction precode and branch prediction during cache line files, decoupled decode / execution code, 3-way AMD64 instruction decoding, sideband stack optimiser, dynamic scheduling and speculative execution.

The new core also features 3-way integer execution and address generation, 3-way 128 bit wide floating point executions, Enhanced 3Dnow! Marchitecture, MMX, SSE, SSE2, SSE3 & SSE4A Single instruction multiple data (SIMD) instruction extensions.

Further the CPU can cope with advanced bit manipulation instructions, super forwarding, prefetch into L1 data cache, deep out of order integer & floating point execution, 8 additional XMM registers (SSE, SSE2, SSE3 and SSE4A) & 8 additional GPRs in 64 Bit mode.

Last but not the least is Enhanced HyperTransport marchitecture. If this is too much for you don’t worry, it is too much for most of us, but we like that the K10 supports SSE4A so it might have a fighting chance in encoding.

  

Last modified on Thursday, 10 May 2007 09:51
blog comments powered by Disqus

 

Facebook activity

Latest Commented Articles

Recent Comments