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Author Topic: 22nm and beyond: News & Analysis  (Read 5775 times)
y eye
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« on: January 26, 2011, 01:39:29 AM »

EUV-litho-era-begins--but-is-it-ready--?

This thread began two years ago. At the time HP was first to take up the Ultra Violet Lithography banner and ASML took the lead building Lithography machinery.
The subject is highly technical and often deep into Theory but it is understandable and very exciting to follow the successes as we march onwards and upwards towards 22nm and beyond.

We have recently witnessed failures by TSMC at 40nm and Intel's success at 32nm. Glofo and TSMC are attempting to skip processes, 32nm and 22nm, in the race to 20nm.
The Gate First scenario has been outperformed by Gate Last at the 32 nanometer high-k metal gate chips by Intel: http://www.youtube.com/watch?v=Oek4ilSsv5M

From   http://www.brion.com/ we can see the documented progress.
Brion is a Robot, an on the floor real time controlling programing Robot.
All of the solutions we have talked about and the ones you can observe at brion.com were and are solved by Brion "The father of the Golden Orb".





Is Lithography ready?
 
The R&D costs to proceed are thinning the players to a few.
They are going for 22nm and beyond with UV Lithography.
   
Editor Note

450-mm simmers

Stop the presses: Semiconductor manufacturers will not be moving to 450-mm wafers for production as quickly as some had targeted.
Prior to the recession, some hoped that 450-mm would be in production by 2015 or 2016. Now, according to IC Insights analyst Trevor Yancey,
450-mm production won't happen until at least 2017 or 2018. Even that seems optimistic.

As has been repeatedly stated here and elsewhere, chip equipment vendors invested big in 300-mm equipment development prior to the last wafer transition,
and they were left holding the bag when a downturn hit and chip makers held off on buying the new tools.
They are understandably squeamish about the possibility of going through all of that again. While the usual suspects—Intel,
Samsung and TSMC—push for 450-mm, equipment vendors realize that these firms are the only potential customers for the tools,
at least initially, and quite possibly ever. But according to VLSI Research CEO G. Dan Hutcheson, equipment makers are actually starting to come around,
prompting "a lot of activity going on in the back channel around 450-mm to indicate that some big news will break next year."
Possibly look for a smattering of 450-mm tool news at this year's Semicon West. Intel is pushing hard for the gear,
but the big question lingers: Who will pay for all of the R&D?
Editor Note: 450-mm simmers and fab schedule slips
 

Analyst: Intel's 450mm not ready for prime-time
Posted: 29 Oct 2010
Keywords: 450-mm wafer fab forecast

As reported, Intel recently confirmed speculation that it will build a new R&D wafer fab in Hillsboro, Ore., and upgrade other existing U.S. facilities
for 22nm production at a total investment of between Rs.28,017.62 crore ($6 billion) and Rs.37,356.82 crore ($8 billion).
The investment will create 800 to 1,000 permanent high-tech jobs and 6,000 to 8,000 construction jobs, Intel (Santa Clara, Calif.) said.
The new development fab in Oregon, to be known as D1X, is slated for R&D start-up in 2013. ''So what do make of this?
We offer two key takeaways and then walk through some additional thoughts on 450mm, as D1X is likely to be 450mm capable,
said C.J. Muse, an analyst with Barclays Capital, in a report.

''With respect to Intel's D1X, our checks reveal that it would likely be 450mm ready (again, 450mm READY), but not yet 450mm capable,'' Muse said.
''What does that mean? It means that it would be facilitized with taller ceilings, enhanced clean room capability
(capable of pumping out a larger volume and filling it with particle free air), and with pedestals able to support and contain any vibration from bigger and heavier tools.
The point being - this does not mean 450mm is ready for prime time, rather Intel is maximising optionality.''

Still, is 450mm ready? No, said Muse. ''We believe 450mm is going to happen, but is likely to involve funding from chip companies.
Equipment companies will not foot the bill alone this time. And it is not ready for prime time, in our view. Not at all, our checks suggest unequivocally,'' he said.

According to Muse-and Sematech-there is much work to be done in 450mm. Chip-consortium Sematech is leading the charge in 450mm, it was noted.

According to Muse, here's what ready for 450mm: 1. requirement guidelines; 2. early design; 3. early prototypes; 4. interoperability test bed; 5. mechanical wafer bank;
6. technology intercept node defined; 7. single crystal wafer bank; and 8. equipment performance metrics.

Here's what is not done: 9. metrology and process equipment development; 10. equipment prototypes; 11. equipment demos; and 12. actual equipment readiness.

Plus, many equipment vendors are reluctant to devise 450mm gear, because it is too expensive and there is no return.
Only a handful of chip makers will build 450mm fabs. Intel, TSMC and Samsung are the few that are pushing for 450mm now.

Cost is the big issue. ''In addition, work at ISMI Sematech suggests, for beam tools like litho, implant and metrology,
the throughput is a function of the area the beam can scan in an hour, the multiplier from 300mm to 450mm is not 2.25+ (2.25+ some additional gain due to edge gains, i.e., more dies can be squeezed in)
but just 1.24 on average and actually just 1.18 for litho,'' Muse said.

''Also, during the same time, the litho industry faces the challenge of making EUV lithography work and overall the semiconductor faces obstacles like a new gate structure,
new materials. So, just yet, we believe it is difficult to see 450mm happening,'' he added.

- Mark LaPedus
EE Times


...01Feb11...

EUV litho era begins, but is it ready?
Mark LaPedus 2/1/2011
 SAN JOSE, Calif.—ASML Holding NV has recently shipped the world's first ''pre-production'' extreme ultraviolet (EUV) lithography tool to a customer, reportedly Samsung Electronics Co. Ltd., sources said.
http://www.eetimes.com/electronics-news/4212771/EUV-litho-era-begins--but-is-it-ready--?cid=NL_EETimesDaily



...07Feb11...

Keywords: EUV lithography tool EUV throughput ASML's second-generation EUV systems

First EUV tool ships amid power, tech concerns
Posted: 07 Feb 2011

Samsung Electronics Co. Ltd was reported to have purchased the world's first "pre-production" extreme ultraviolet (EUV) lithography tool from ASML Holding NV.
However, what experts are more concerned about is whether EUV is ready for prime time. To date, the power source and other technologies for EUV have yet to be finalized.
Sources also revealed that the throughput still poses challenges as the tool only manages 10 to 12 wafers per hour, a figure way below that required by high-volume production fabs.

In its recent results, ASML said it shipped the first of its second-generation EUV systems, the NXE:3100, to an undisclosed customer manufacturing site.
The NXE:3100 will offer a resolution of 27nm with a numerical aperture (NA) of 0.25, overlay of less than 4.5nm and a throughput of 60 wafers per hour.

A "pre-production" EUV scanner from ASML runs about 60 million Euros, or $86.9 million, per unit. Some say that price tag could hit $125 million when ASML ships a production-worthy tool.

http://www.eetasia.com/ART_8800633925_480200_NT_24e02b7b.HTM?click_from=8800071881,9949906143,2011-02-07,EEOL,ARTICLE_ALERT


...10Feb11...






http://www.asml.com/doclib/press/asml_20100812_Images_Summer_Edition-final.pdf



...11Feb11

February 09, 2011                                      
Researchers at Harvard and MITRE produce world’s first programmable nanoprocessor

Nanowire tiles can perform arithmetic and logical functions and are fully scalable

Source: CONTACT: Caroline Perry, 617-496-3815   http://www.seas.harvard.edu/news-events/press-releases/nanoprocessor
Cambridge, Mass. – February 9, 2011 –

The work was enabled by advances in the design and synthesis of nanowire building blocks.
These nanowire components now demonstrate the reproducibility needed to build functional electronic circuits,
and also do so at a size and material complexity difficult to achieve by traditional top-down approaches.

Moreover, the tiled architecture is fully scalable, allowing the assembly of much larger and ever more functional nanoprocessors.

“For the past 10 to 15 years, researchers working with nanowires, carbon nanotubes,
and other nanostructures have struggled to build all but the most basic circuits,
in large part due to variations in properties of individual nanostructures,” says Lieber,
the Mark Hyman Professor of Chemistry. “We have shown that this limitation can now be overcome and are excited about prospects of
exploiting the bottom-up paradigm of biology in building future electronics.”

An additional feature of the advance is that the circuits in the nanoprocessor operate using very little power, even allowing for their miniscule size,
because their component nanowires contain transistor switches that are “nonvolatile.”

This means that unlike transistors in conventional microcomputer circuits, once the nanowire transistors are programmed,
they do not require any additional expenditure of electrical power for maintaining memory.

“Because of their very small size and very low power requirements, these new nanoprocessor circuits are building blocks that can control and
enable an entirely new class of much smaller, lighter weight electronic sensors and consumer electronics,” says co-author Shamik Das,
the lead engineer in MITRE’s Nanosystems Group.


“This new nanoprocessor represents a major milestone toward realizing the vision of a nanocomputer that was first articulated more than 50 years ago by
physicist Richard Feynman,” says James Ellenbogen, a chief scientist at MITRE.

Co-authors on the paper included four members of Lieber’s lab at Harvard: Hao Yan (Ph.D. '10), SungWoo Nam (Ph.D. '10), Yongjie Hu (Ph.D. '10),
and doctoral candidate Hwan Sung Choe, as well as collaborators at MITRE.

...11Feb11...

Lab Partnership Develops Programmable Nanoprocessor
By RADHIKA JAIN, CRIMSON STAFF WRITER http://www.thecrimson.com/article/2011/2/11/researchers-system-nano-lab/
Published: Friday, February 11, 2011


###


...11April11...

                    

  http://www.eetasia.com/ART_8800640001_480200_NT_60b931db.HTM?click_from=8800077253,9949906143,2011-04-11,EEOL,ARTICLE_ALERT


...16May11...


Business News
TSMC joins Sematech, cites 450-mm R&D
May 16, 2011 | Peter Clarke | 222907379   http://www.electronics-eetimes.com/en/tsmc-joins-sematech-cites-450-mm-r-d.html?cmp_id=7&news_id=222907379&vID=662#
Foundry Taiwan Semiconductor Manufacturing Co. Ltd. has announced
that it has decided to join Sematech, the international consortium
of semiconductor manufacturers, as a core member.

TSMC (Hsinchu, Taiwan) has long been a core member at a rival research collaboration, hosted by IMEC (Leuven, Belgium),
where it works with most of the world's leading semiconductor companies. The company has now opted to also join Sematech.

TSMC said it would collaborate on semiconductor research and development for IC process technologies for the 20-nm generation and beyond,
including extreme ultra-violet (EUV) lithography, 3-D interconnects, metrology, novel materials and device structures,
and to develop critical infrastructure vital for next-generation manufacturing, including the transition to the 450-mm wafer size for production.

Sematech's other core members include GlobalFoundries, Hewlett Packard, IBM, Intel, Samsung, UMC,
and the College of Nanoscale Science and Engineering (CNSE) at Albany, New York.

"This complementary cooperation leverages Sematech's collaborative approach to lead critical industry technology transitions,
with TSMC’s position as an industry leader in advanced technology development and manufacturing," said Jack Sun, CTO at TSMC, in a statement.

"TSMC will be an important partner in accelerating the progress of R&D innovations and manufacturing solutions in leading edge technologies,"
said Dan Armbrust, president and CEO of Sematech.


...21June11...

The 28nm node is TSMC's most energy-efficient and high-performance process technology family.

The 28nm Low Power (LP) process was the first in the foundry sector to reach production.
The 28 High Performance (HP) is the first high-k metal gate process technology and features superior speed and performance.
The 28 High Performance, Low Power (HPL) is our lowest-leakage process and adopts the same gate stack
as found in the HP technology while meeting more stringent low leakage requirements. The 28 High Performance,
Mobile (HPM) process is specifically designed for mobile computing, providing for higher performance than 28HP with leakage similar to 28LP.
        
         http://www.tsmc.com/advanced_technology_AD/28nm.htm

         http://www.tsmc.com/english/dedicatedFoundry/manufacturing/gigafab.htm


...23June...

SuVolta creates new transistor option for 20nm
Ron Wilson  http://www.eetimes.com/design/eda-design/4217178/SuVolta-creates-new-transistor-option-for-20nm?cid=NL_Embedded&Ecosystem=embedded
6/22/2011 1:13 PM EDT

SuVolta, a startup process IP company with deep roots in device design and modeling, has developed a new transistor that could challenge finFETs and SoI at 20nm and below,
as the conventional planar MOSFET begins to run out of steam. Built in a conventional process but offering channel mobility approaching that of intrinsic silicon,
the PowerShrink technology raises the prospect of power savings on the order of a factor of five, lower operating voltages, vastly reduced threshold variations, and more to come.

The key to the technology, according to SuVolta CTO Scott Thompson, is that the transistor is in every way like any other planar MOSFET—with one huge difference.
The PowerShrink device has a shallow, updoped channel that operates in deeply-depleted mode. In this sense, the device is more like a fully-depleted SoI (FDSoI) MOSFET.
But the SoI device requires a special FDSoI wafer that has only a 10-15nm layer of silicon over a buried layer of oxide.

In contrast, SuVolta’s device creates the same ultra-thin 5nm-thick channel by implanting few-atoms-thick dopant layers beneath the channel.
These implants apparently form a buried junction that, when properly biased, depletes the thin active region of the channel almost completely.
The result is a device that exhibits the very low leakage, very high mobility, and very low threshold variation of FDSoI, but on a conventional wafer and process.








« Last Edit: June 23, 2011, 07:42:18 PM by y eye » Logged

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